The concept of buffer layers is well-known and widely used in heteroepitaxy of semiconductors. They are designed to alleviate interfacial stress and defect formation or to promote growth of certain phases or 2D morphology. For highly mismatched systems, the concept of graded buffer layers was first proposed at RCA in 1966, and most efforts to date have been designed to find solutions to specific problems rather than a global pathway to semiconductor integration. From all integration schemes, the integration of III-V and II-VI semiconductors with silicon would have the most favorable impact on functionality, miniaturization and production cost.
Low Al content AlGaAs compounds possess lattice constants close to that of Ge. As such, Ge seems to be a reasonable pathway to monolithic integration of some arsenide-based devices with Si. Although Si and Ge are closely related, direct epitaxy of Ge on Si produces copious defects in the Ge layer due to a significant lattice and thermal mismatch. To alleviate this problem, research in recent years has focused on graded Si1-xGex buffer layers grown on Si(100). In this case, a thick Si1-xGex interlayer is graded compositionally up to 100% Ge to create a virtual substrate that is nearly lattice matched to GaAs. A graded layer thickness in excess of 10 μm is required to achieve threading dislocation densities in the 106 per cm2 range, and a post growth chemical mechanical polishing (CMP) step is necessary to produce a smooth surface prior to subsequent growth.
While the above approach is relatively straightforward it poses several limitations: (1) the addressable lattice parameter space is limited to a narrow range between Si and Ge, thus allowing lattice matching of only three compounds (GaAs, GaP, and AIP); (2) the process requires thick buffer layers grown at a relatively high temperature, which causes additional defect formation due to thermal mismatch; (3) a post-growth, CMP planarization step is mandatory; and (4) threading defect densities are in the 106 per cm2 range, which is detrimental to most advanced compound devices; a reduction in defect density of two to three orders of magnitude is needed.
Thus, improved materials and methods for integration of III-V and II-VI semiconductors with silicon are needed in the art.